1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a dynamic random access memory (which will be referred to as a xe2x80x9cDRAMxe2x80x9d hereinafter).
2. Description of the Background Art
In recent years, demands for semiconductor memory devices have been rapidly increased owing to rapid and wide spread of information equipments such as computers. Regarding a function, devices having a large-scale storage capacity and a high operation speed have been demanded. In view of this, technical development has been made for improving a density, a responsibility and a reliability of semiconductor memory devices.
The DRAM is a kind of semiconductor memory device allowing random input/output of storage information. The DRAM is generally formed of a memory cell array, which is a storage region storing large storage information, and a peripheral circuitry required for external input and output.
FIGS. 37A and 37B show a DRAM having conventional memory cells of a stacked type. Referring to FIGS. 37A and 37B, a p-type semiconductor substrate 1 is provided at its main surface with a p-type impurity region 3. A field insulating film 2 and p-type impurity regions 4a and 4b are formed on p-type impurity region 3. p-type impurity regions 4a and 4b are provided for controlling threshold voltages of transistors.
Lightly doped n-type impurity regions 5 which are spaced from each other are formed at the surface of p-type impurity region 4a. Lightly doped n-type impurity regions 5 and heavily doped n-type impurity regions 7 are formed at spaced portions of the surface of p-type impurity region 4b. 
Gate electrodes 12 are formed on the main surface of semiconductor substrate 1 in the memory cell portion with gate insulating films 8b therebetween, respectively, and gate electrodes 12 are also formed on the main surface of semiconductor substrate 1 in the peripheral circuitry with gate insulating films 9 therebetween, respectively. Gate insulating films 8 and 9 are equal in thickness. Each gate electrode 12 is formed of a polycrystalline silicon film 10 and a WSi film 11.
A TEOS (Tetra Btyle Ortho Silicate) is formed on gate electrode 12, and a side wall insulating film 14 is formed on the side wall of gate electrode 12. Gate electrodes 12 are covered with an interlayer insulating film 15 extending through the memory cell portion and the peripheral circuitry. Contact holes 15a and 15b are formed in interlayer insulating film 15.
A bit line 16a having a portion located within contact hole 15a extends on interlayer insulating film 15, and an interconnection layer 16b having a portion located within contact hole 15b extends on interlayer insulating film 15. Bit line 16a and interconnection layer 16b are covered with an interlayer insulating film 17. Contact holes 17a which reach lightly doped n-type impurity regions 5, respectively, extend through interlayer insulating films 17 and 15.
Storage nodes 18 which have portions located within contact holes 17a, respectively, extend on interlayer insulating film 17. A surface of each storage node 18 is covered with a capacitor insulating film 19, over which a cell plate 20 is formed. Cell plate 20, capacitor insulating film 19 and storage node 18 form a capacitor 21.
Capacitors 21 and interlayer insulating film 17 are covered with an interlayer insulating film 22. The peripheral circuitry is provided with a contact hole 23a extending through interlayer insulating films 22 and 17, a contact hole 23b reaching corresponding gate electrode 12 and a contact hole 23c reaching heavily doped n-type impurity region 7. Metal interconnections 24b, 24c and 24d, which have portions located within contact holes 23a, 23b and 23c, respectively, extend on interlayer insulating film 22. In the memory cell portion, metal interconnections 24a are formed on interlayer insulating film 22.
In recent years, elements have been further miniaturized, and the thicknesses of gate insulating films 8b and 9 have been reduced. Particularly, a concentration of p-type impurity region 4a for controlling a threshold voltage of the transistor in the memory cell portion have been increased in accordance with the above reduction in thickness. Consequently, such a problem is becoming manifest that a leak current at a pn-junction (which will be merely referred to as a xe2x80x9cjunction leak currentxe2x80x9d hereinafter) increases.
According to the isolating structure of the trench type shown in FIGS. 37A and 37B, there is a tendency that a stress concentrates at the vicinity such as a region A and B of the periphery of field insulating film 2. In this case, the junction leak current cannot be suppressed sufficiently because the source/drain of the transistor in the memory cell portion are formed of only lightly doped n-type impurity region 5. Further, an etching damage is liable to occur at region A when side wall insulating film 14 is etched. This also becomes a cause of generation of the junction leak current. Such a junction leak current may destroy data stored in storage node 18.
Further, the foregoing increase in concentration of p-type impurity region 4a for the threshold voltage control causes disadvantageous increase in sheet resistance of lightly doped n-type impurity region 5.
The invention has been developed to overcome the above problems. An object of the invention is to reduce a junction leak current.
According to an aspect, a semiconductor device of the invention includes a first transistor having a gate insulating film of a first thickness, and a second transistor having a gate insulating film of a second thickness smaller than the first thickness. At least one of source/drain of the first transistor is formed of a first lightly doped region and a first heavily doped region. At least one of source/drain of the second transistor includes a second lightly doped region and a second heavily doped region higher in concentration than the first heavily doped region.
As described above, the gate insulating film of the first transistor is thicker than the gate insulating film of the second transistor so that it is possible to lower a concentration of an impurity region provided for controlling a threshold voltage of the first transistor. Thereby, it is possible to lower a junction leak current. Since at least one of source/drain of the first transistor has the first heavily doped region, the junction leak current can be lower than that in the prior art even if a field insulating film is adjacent to the source/drain. Further, provision of the forgoing first heavily doped region can reduce the sheet resistance of the source/drain. Since the second transistor has the second heavily doped region of a higher concentration than the first heavily doped region, the sheet resistance of the source/drain can be sufficiently reduced.
At least one of the source/drain of the second transistor may have a medium-doped region having a concentration higher than the second lightly doped region and lower than the second heavily doped region.
By providing the medium-doped region as described above, it is possible to surround the second heavily doped region by the medium-doped region. Thereby, it is possible to avoid direct contact of the second heavily doped region with an impurity region of a different conductivity type so that concentration of an electric field can be suppressed. This also contributes to reduction in junction leak current.
Preferably, the semiconductor device includes a memory cell portion for storing data and a peripheral circuit portion for external input/output. In this case, it is preferable that the memory cell portion includes the first transistor, and the peripheral circuit portion includes the second transistor.
The above structure in which the memory cell includes the first transistor can reduce the junction leak current at the memory cell portion. In the peripheral circuitry, it is possible to provide the transistor having source/drain of a reduced sheet resistance and thus having a high performance.
A diffusion depth (a depth of the peak concentration) of the second heavily doped region is preferably smaller than a diffusion depth of the medium-doped region.
Thereby, it is possible to surround the second heavily doped region by the medium-doped region, and thereby the junction leak current can be reduced as described above.
A field insulating film may be formed in contact with the first heavily doped region. In this structure, the first and second transistors are covered with an interlayer insulating film having a contact hole reaching the first heavily doped region and the field insulating film, and a concavity is formed at the field insulating film located immediately under the contact hole. A storage node is formed in the concavity and on the first heavily doped region.
By formation of the field insulating film in contact with the heavily doped region, it is possible to reduce the junction leak current at the vicinity of the periphery of the field insulating film. Further, by formation of the concavity at the field insulating film located immediately under the contact hole, it is possible to remove the field insulating film from a portion where a stress is liable to concentrate. This also contributes to reduction in junction leak current. By provision of the concavity, it is possible to increase a contact area between the storage node and the heavily doped region. Thereby, a contact resistance can be improved.
According to another aspect, a semiconductor device of the invention includes a semiconductor substrate having a main surface, first and second impurity regions for threshold voltage control, and first and second transistors. The first impurity region has a peak concentration at a position of a first depth from the main surface. The second impurity region is spaced from the first impurity region, and has a peak concentration at a position of a second depth larger than the first depth. The first transistor is formed on the first impurity region, and has a gate insulating film of a first thickness. The second transistor is formed on the second impurity region, and has a gate insulating film of a second thickness smaller than the first thickness.
By employing the first transistor having the gate insulating film thicker than the gate insulating film of the second transistor, it is possible to reduce the concentration of the first impurity region. Further, by locating the peak concentration of the first impurity region at the position shallower than the peak concentration of the second impurity region, it is possible to reduce further the concentration of the first impurity region. Thereby, the junction leak current can be reduced further effectively.
A third impurity region lower in concentration than the first impurity region may be formed under the first impurity region. It is preferable that the first transistor has a pair of first source/drain, and at least one of the first source/drain reaches the third impurity region. It is preferable that the second transistor has a pair of second source/drain having diffusion depths smaller than the second depth.
Owing to the above structure in which at least one of the first source/drain reaches the position deeper than the first impurity region, it is possible to reduce a contact area of the first impurity region with respect to the source/drain. Thereby, the junction leak current can be further reduced.
According to still another aspect, a semiconductor device of the invention includes a first transistor having a gate insulating film of a first thickness, and a second transistor having a gate insulating film of a second thickness smaller than the first thickness. The first transistor has first and second impurity regions having relatively large first diffusion depth and relatively small second diffusion depth and forming source/drain, respectively. The second transistor has third and fourth diffusion regions having diffusion depths smaller than the first diffusion depth and not smaller than the second diffusion depth, and forming source/drain, respectively.
By employing the first transistor having the gate insulating film thicker than the gate insulating film of the second transistor as described above, the junction leak current can be reduced. Further, owing to the structure wherein only the first diffusion region has the large diffusion depth, deterioration in resistance against punch through can be suppressed in a subminiaturized structure, compared with a structure wherein both the first and second impurity regions have equal diffusion depths.
A concentration of the first impurity region having the first diffusion depth is preferably higher than a concentration of the second impurity region. In this structure, a field insulating film may be formed in contact with the first impurity region.
By deeply forming the first impurity region having the relatively high impurity concentration as described above, the periphery of the field insulating film can be covered with the first impurity region. Thereby, it is possible to reduce a junction leak current at the vicinity of the bottom of the field insulating film.
According to yet another aspect of the invention, a semiconductor device of the invention includes first and second transistors, an interlayer insulating film, a plug electrode, a bit line, and first and second metal silicide. The first transistor is formed on a main surface of a semiconductor substrate, and has first source/drain. The second transistor is formed on the main surface with a space from the first transistor, and has second source/drain. An interlayer insulating film covers the first and second transistors, and has a contact hole reaching one of the first source/drain. The plug electrode is formed in the contact hole. The first metal silicide is formed on surfaces of the second source/drain. The bit line is formed on the plug electrode with a second metal silicide therebetween.
Since a metal film for forming the metal silicide is usually formed by a sputtering method, it is difficult to form a thick metal silicide at the bottom of the contact hole. In contrast to this, the second metal silicide can be thick because the second metal silicide is formed on the plug electrode as described above. Meanwhile, it is possible to form thick metal silicide films on the surfaces of the second source/drain of the second transistor by a known method, respectively. By forming the thick metal silicide as described above, a heat resistance can be improved. Thereby, it is possible to avoid disadvantages such as deterioration in junction leak current characteristic and increase in contact resistance, which may be caused by deterioration of the metal silicide due to a heat treatment at about 800xc2x0 C. or more.
A method of manufacturing a semiconductor device of an aspect of the invention includes the following steps. First and second gate electrodes of first and second transistors are formed on a main surface of a semiconductor substrate with a space between each other. A nitride film covering the first and second gate electrodes is formed. Sources and drains of the first and second transistors are formed. An interlayer insulating film covering the nitride film is formed. A first contact hole reaching one of the source/drain of the first transistor is formed in the interlayer insulating film. A second contact hole reaching one of the source/drain of the second transistor and a third contact hole extending through the interlayer insulating film and the nitride film to the second gate electrode are formed in the interlayer insulating film. A bit line connected to one of the source/drain of the first transistor through the first contact hole as well as first and second interconnections extending in the second and third contact holes, respectively, are formed.
If elements are further miniaturized and the first contact hole connecting the bit line to the source/drain is formed in a self-aligned manner with respect to the gate electrode, it is preferable to form the first contact hole in a step other than that of forming the second and third contact holes. This is because of such a fact that the first contact hole is partially defined by the nitride film on a side wall of the first gate electrode during formation of the first contact hole in contrast to the third contact hole penetrating the nitride film. By forming the first contact hole in the step other than the step of forming the second and third contact holes, it is possible to provide the respective contact holes having desired sizes and forms. Further, the plug electrode can be formed only in the first contact hole. Owing to formation of this plug electrode, a thick metal silicide can be formed at the surface thereof so that deterioration in junction leak current characteristic can be effectively suppressed as described above.
The source/drain of the second transistor may have a heavily doped region, and the step of forming the source/drain of the second transistor may include the step of forming first metal silicide at the surface of the heavily doped region. The step of forming the bit line may include the steps of forming the plug electrode in the first contact hole, forming second metal silicide at the surface of the plug electrode, and forming the bit line on the second metal silicide.
By forming the first metal silicide at the surface of the heavily doped region in the source/drain of the second transistor, it is possible to reduce a sheet resistance of the source/drain of the second transistor. Further, by forming the plug electrode in the first contact hole, it is possible to suppress deterioration in junction leak current characteristic as described above.
According to yet another aspect, a method of manufacturing a semiconductor device of the invention includes the following steps. First and second electrodes of first and second transistors are formed on a main surface of a semiconductor substrate with a space between each other. A nitride film covering side walls of the first and second gate electrodes is formed. First impurity regions are formed at opposite sides of the first and second gate electrodes. An interlayer insulating film covering the first and second gate electrodes is formed. A contact hole reaching one of the first impurity regions of the first transistor and the nitride film is formed in the interlayer insulating film. A second impurity region overlapping with the one of the first impurity regions of the first transistor and having a higher concentration than the first impurity region is formed by introducing impurity into the semiconductor substrate through the contact hole. A storage node electrically connected to the second impurity region through the contact hole is formed.
By forming the second impurity region as described above, it is possible to increase selectively a diffusion depth of one of the source/drain connected to the storage node. Thereby, a junction leak current can be effectively reduced in a structure wherein the field insulating film is formed in contact with the source/drain on the side provided with the second impurity region. Since the source/drain on the side not provided with the second impurity region can be shallow, deterioration in resistance against punch through can be suppressed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.